Semiconductor integrated circuit (IC) technology is continually progressing to circuit layouts having smaller feature sizes as well as increased density. As a result of this continuous progression, a photolithography system is more sensitive to flatness of a mask having circuit patterns to be transferred to a semiconductor wafer. It is also necessary to evaluate focal plane error and tune a lens module of the photolithography system for enhanced resolution and reduced deformation. Current practice involves measuring reticle shape correction (RSC) marks on a mask. The RSC marks are disposed around (but not in) the main pattern of the mask. The flatness data of the mask within the main pattern region cannot be directly measured. Instead, they are simulated based on the flatness data on these peripheral regions surrounding the main pattern region. This results in inaccurate overall measurements and adversely limits any resulting resolution improvement.
It is desired, therefore, to provide a method and apparatus for measuring mask flatness and compensating focal plane error more accurately and effectively.